Within an integrated circuit such as a system-on-a-chip (SoC), it is conventional to segregate subsystems into corresponding power domains. Each subsystem's power domain has its own power supply rail for supplying a power supply voltage to the subsystem's devices, including its embedded memories. Although the power supply rails are associated with bypass capacitors to assist in maintaining the power supply voltage, the sudden switching on of a plurality of embedded memories within a given power domain causes its power supply voltage to momentarily droop due to an in-rush of current into the switched-on embedded memories. If this droop is too pronounced, the power island resets and must boot up again.
To prevent such mishaps, it is thus conventional to sequence the power-up of the embedded memories to reduce the voltage droop to an acceptable level that ensures normal operation. For example, it is conventional to use timed bits that stage the turn-on of various memory banks within an array of memories. Alternatively, the various memory banks within an array may have their power sequencing through a daisy chain of buffers. In addition, the power sequencing may be determined through different sized switches or slew control. But such conventional in-rush mitigation requires the circuit designer to lock the sequencing of the memories and the delays from the buffer chains prior to the instantiation of the device. After tape-out, it may be discovered that process variations and other factors produce more in-rush current than expected despite the memory sequencing such that the voltage droop on the rail causes circuit operation errors. This is quite costly as the SoC must then be redesigned. The designer will thus tend to err on providing too much delay in the memory sequencing, which slows operation and consumes power.
Accordingly, there is a need in the art for improved current in-rush mitigation during power up sequencing of embedded memories.